1. Field of the Invention
The disclosed embodiments of the present invention relate to memory management, and more particularly, to a management method of a virtual-to-physical address translation system, which uses a part of bits of a virtual address as an index, and a related virtual-to-physical address translation system.
2. Description of the Prior Art
A conventional memory management unit employs a translation lookaside buffer (TLB) to improve search efficiency of a page table. For example, a TLB employed in a Microcomputer without Interlocked Pipeline Stages (MIPS) may have a plurality of entries (e.g. 64 entries) for fast lookup, wherein each entry may store a virtual-to-physical address translation associated with a virtual address and a physical address.
During a lookup process of the aforementioned TLB, it is necessary to compare a virtual address to be looked up with a virtual address stored in each entry (i.e. fully-associative mapping). In other words, a plurality of comparator circuits are required. Hence, if the number of entries of the TLB is increased to improve system performance, a circuit area of the TLB increases, thus lowering processing speed. However, if the number of entries of the TLB is decreased, the system performance is degraded (e.g. probability of a TLB miss increases).
Thus, a virtual-to-physical address translation system, which may improve system performance without scarifying a circuit area and a processing speed, is needed.